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1. There are multiple routes to reach from node 1 to node 2, as shown in the network. The cost of the travel on an edge between nodes is given in rupees. Nodes ‘a’, ‘b’, ‘c’, ‘d’, ‘e’, and ‘f’ are toll booths. The toll price at toll booths marked ‘a’ and ‘e’ is Rs. 200, Rs. 100 for the other toll booths. Which is the cheapest route from node 1 to 2?

Options

A : 1-b-2

B : 1-f-e-2

C : 1-a-c-2

D : 1-f-b-2

2. The total revenue of a company during 2014-2018 is shown in the graph. If the expenditure of the company in each year is 500 million rupees, then the aggregate profit loss (in percentage) on the total expenditure of the company during 2014-2018 is _______

Options

A : 20% profit

B : 16.67% loss

C : 16.67 profit

D : 20% loss

3. Select the words that fits the analogy: Cook : Cook :: Fly : ______

Options

A : Flew

B : Flighter

C : Flyer

D : Flying

4. Raman is confident of speaking English _____ six months as he has been practicing regularly ______ the last three weeks.

Options

A : within, for

B : during, for

C : for, in

D : for, since

5. Goods and Services Tax (GST) is an indirect tax introduced in India in 2017 imposed on the supply of goods and services, and it subsumes all indirect taxes except few. It is a destination-based tax imposed on goods and services used, and it is not imposed the point of origin from where goods come. GST also has a few components spec*** state governments, central government and Union Territories (UT’s). Which one of the following statements can be inferred from the given passage?

Options

A : GST does not have a component specific to UT.

B : GST is imposed at the point of usage of goods and services.

C : GST is imposed on the production of goods and services.

D : GST includes all indirect taxes.

46. Let R be the set of all binary relations on the set {2, 3}. Suppose a relation chosen from R at random. The probability that the chosen relation is reflex (round off to 3 decimal places) is ________.

Options

A : 0.125

B : 0.102

C : 0.215

D : 0.152

47. A direct mapped cache memory of 1 MB has a block size of 256 bytes. The cache has an access time of 3 ns and a hit rate of 94%. During a cache miss, it takes 20 ns to bring the first word of a block from the main memory, while each subsequent word takes 5 ns. The word size is 64 bits. The average memory access time in ns (round off to 1 decimal place) is _______.

Options

A : 13

B : 13.5

C : 12

D : 12.5

48. Consider the following grammar. S → aSB | d B → b The number of reduction steps taken by a bottom-up parser while accepting string aaadbbb is ______ .

Options

A : 6

B : 7

C : 8

D : 4

49. If there are m input lines and n output for a decoder that is used to unique address a byte-addressable 1 KB RAM, then the minimum value of m + n is _____

Options

A : 1024

B : 10

C : 1030

D : 1034

50. A multiplexer is placed between a group of 32 register and an accumulator to regulate data movement such at that any given point in time the content of only one register will move to the accumulator. The minimum number of select lines needed for the multiplexer is ______ .

Options

A : 5

B : 4

C : 6

D : 3

51. Consider the following C program.

Options

A : 19

B : 20

C : 18

D : 20

52. Consider the following language. number of a’s in x is divisible by 2 but not divisible by 3 The minimum number of states in a DFA that accepts L is ____.

Options

A : 5

B : 4

C : 6

D : 3

53. A processor has 64 registers and uses 16-bit instruction format. It has two type instruction: I-type and R-type. Each I-type instruction contains an opcode, a register name, and a 4-bit immediate value. Each R-type instruction contains an opcode and two register names. If there are 8 distinct I-type opcodes, then the maximum number of distinct R-type opcodes is _____.

Options

A : 14

B : 13

C : 12

D : 11

54. The number of permutations of the characters in LILAC so that no characters appears in its original position, if the two L’s are indistinguishable, is _______.

Options

A : 11

B : 10

C : 13

D : 12

55. Graph G is obtained by adding vertex s to K 3,4 and making s adjacent to every vertex of K 3,4 . The minimum number of colours required to edge-colour is G______.

Options

A : 7

B : 6

C : 5

D : 8

56. Consider a paging system that uses a 1-level page table residing in main memory and a TLB for address translation. Each main memory access takes 100 ns. TLB lookup takes 20 ns. Each page transfer to/from the disk takes 5000 ns. Assume that the TLB hit ratio is 95%, page fault rate is 10%. Assume that for 20% of the total page faults, a dirty page has to be written back to disk before required page is read in from disk. TLB update time is negligible. The average memory access time is ns (round off to 1 decimal places) is ______.

Options

A : 755

B : 725

C : 155

D : 154.5

57. Consider a graph G = (V, E), where V = {v 1 , v 2 , …, v 100 }, E = {(v i , v j )|1≤i≤j≤100}, and weight of the edge (v i , v j ) is |i – j|. The weight of the minimum spanning tree of G is _____.

Options

A : 99

B : 100

C : 98

D : 110

58. For n > 2, let a ∈ {0, 1} n be a non-zero vector. Suppose that x is chosen uniformly at random form (0,1)n. Then, the probability that is an number is _______ .

Options

A : 0.5

B : 0.25

C : 0.3

D : 0.45

59. Consider the array representation of a binary min-heap containing 1023 element. The minimum number of comparisons required to find the maximum in the heap is ______.

Options

A : 511

B : 512

C : 510

D : 500

60. Consider a non-pipelined processor operating at 2.5 GHz. It takes 5 clock cycles to complete an instruction. You are going to make a 5-stage pipeline out of this processor. Overheads associated with pipelining force you to operate the pipeline processor at 2 GHz. In a given program, assume that 30% are memory instructions, 60% are ALU instructions and the rest are branch instruction. 5% of the memory instructions cause stalls of 50 clock cycles each due to cache misses and 50% of the branch instructions cause stalls of 2 cycles each. Assume that there are no stalls associated with the execution of ALU instructions. For this program, the speedup achieved by the pipelined processor over the non-pipeline processor (round off to 2 decimal places) is ______.

Options

A : 2.15

B : 2.16

C : 2.14

D : 2.10

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