### 57. Consider a RISC machine where each instruction is exactly 4 bytes long. Conditional and unconditional branch instructions use PC- relative addressing mode with Offset specified in bytes to the target location of the branch instruction. Further the Offset is always with respect to the address of the next instruction in the program sequence. Consider the following instruction sequence.

### 58. In a RSA cryptosystem a participant A uses two prime numbers p = 13 and q = 17 to generate her public and private keys. If the public key of A is 35. Then the private key of A is ______.

### 59. Let A be an array of 31 numbers consisting of sequence of 0’s followed by a sequence of 1’s. The problem is to find the smallest index i that A[i] is 1 by probing the minimum numbers of locations in A. The worst case number of probes performed by an optimal algorithm is _____.

### 60. Instructions execution in a processor is divided into 5 stages. Instruction Fetch (IF), Instruction Decode (ID), Operand Fetch (OF), Execute (EX), and Write Back (WB), These stages take 5,4,20, 10 and 3 nanoseconds (ns) respectively. A pipelined implementation of the processor requires buffering between each pair of consecutive stages with a delay of 2ns. Two pipelined implementations of the processor are contemplated. (i) a naïve pipeline implementation (NP) with 5 stages and (ii) an efficient pipeline (EP) where the OF stage id divided into stages OF1 and OF2 with execution times of 12 ns and 8 ns respectively. The speedup (correct to two decimals places) achieved by EP over NP in executing 20 independent instructions with no hazards is _____.