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Computer System Architecture - Digital Logic Circuits - Combinational Circuits Online Exam Quiz

Important questions about Computer System Architecture - Digital Logic Circuits - Combinational Circuits. Computer System Architecture - Digital Logic Circuits - Combinational Circuits MCQ questions with answers. Computer System Architecture - Digital Logic Circuits - Combinational Circuits exam questions and answers for students and interviews.

1. In which of the following gates, the output is 1, if and only if at least one input is 1?

Options

A : NOR

B : AND

C : OR

D : NAND

2. The time required for a gate or inverter to change its state is called

Options

A : Rise time

B : Decay time

C : Propagation time

D : Charging time

3. The time required for a pulse to change from 10 to 90 percent of its maximum value is called

Options

A : Rise time

B : Decay time

C : Propagation time

D : Operating speed

4. The maximum frequency at which digital data can be applied to gate is called

Options

A : Operating speed

B : Propagation speed

C : Binary level transaction period

D : Charging time

5. What is the minimum number of two-input NAND gates used to perform the function of two input OR gate ?

Options

A : one

B : two

C : three

D : four

46. Which one of the following logic expression is incorrect?

Options

A : 1 ⊕ 0 = 1

B : 1 ⊕ 1 ⊕ 0 = 1

C : 1 ⊕ 1 ⊕ 1 = 1

D : 1 ⊕ 1 = 0

48. The black box in the following figure consists of a minimum complexity circuit that uses only AND,OR and NOT gates. The function f (x,y,z) = 1 whenever x , y are different and 0 otherwise. In addition the 3 inputs x,y,z are never all the same value. Which of the following equation lead to the correct design for the minimum complexity circuit?

Options

A : x'y + xy'

B : x + y'z

C : x'y'z' + xy'z

D : xy + y'z + z'

49. If A ⊕ B = C, then

Options

A : A ⊕ C = B

B : B ⊕ C = A

C : A ⊕ B ⊕ C = 0

D : Both (a) & (b)

50. To make the following circuit a tautology ? marked box should be

Options

A : OR gate

B : AND gate

C : NAND gate

D : EX-OR GATE

51. For the circuit shown for AB = 00, AB = 01, C, S values respectively are

Options

A : 0 , 0 and 0, 1

B : 0, 0 and 1, 0

C : 0, 1 and 0, 0

D : 1, 0 and 0, 0

52. What logic gate is represented by the circuit shown below?

Options

A : NAND

B : NOR

C : AND

D : EQUIVALENCE

53. The circuit shown below is the

Options

A : Full adder

B : Full subtractor

C : Parity checker

D : None of these

54. In the following gate network which gate is redundant?

Options

A : Gate no. 1

B : Gate no. 2

C : Gate no. 3

D : Gate no. 4

55. The combinational circuit given below is implemented with two NAND gates. To which of the following individual gates is its equivalent?

Options

A : NOT

B : OR

C : AND

D : XOR

56. What logic function is performed by the circuit shown below?

Options

A : Ring counter

B : Ripple counter

C : Full adder

D : Half adder

57. What is the Boolean expression for the following circuit?

Options

A : F(A, B) = ( A + B' )' . ( B + A' )'

B : F( A, B ) = 1 ( Tautology )

C : F( A, B ) = ⊕ ( inconsistency)

D : F ( A, B ) = A ⊕ B ( A exclusive OR'ed with B)

58. In the circuit shown below, which logic function does this circuit generate?

Options

A : AND

B : NOR

C : NAND

D : OR

59. Output of the following circuit is

Options

A : 0

B : 1

C : x

D : x'

60. A small dot or circle printed on top of an IC indicates

Options

A : V cc

B : G nd

C : Pin 14

D : Pin 1

61. The number of two input multiplexers required to construct a 210 input multiplexer is,

Options

A : 31

B : 10

C : 127

D : 1023

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