## Exam-GK-MCQ-Questions.Com

Home - Digital Electronics - Combinational Logic Analysis

# Combinational Logic Analysis Online Exam Quiz

Important questions about Combinational Logic Analysis. Combinational Logic Analysis MCQ questions with answers. Combinational Logic Analysis exam questions and answers for students and interviews.

Options

A : 1

B : 2

C : 3

D : 4

Options

A : 10111100

B : 10111000

C : 11100111

D : 00011101

### 3. The following waveform pattern is for a(n) ________.

Options

A : 2-input AND gate

B : 2-input OR gate

C : Exclusive-OR gate

D : None of the above

### 4. One positive pulse with t w = 75 µs is applied to one of the inputs of an exclusive-OR circuit. A second positive pulse with t w = 15 µs is applied to the other input beginning 20 µs after the leading edge of the first pulse. Which statement describes the output in relation to the inputs?

Options

A : The exclusive-OR output is a 20 µs pulse followed by a 40 µs pulse, with a separation of 15 µs between the pulses.

B : The exclusive-OR output is a 20 µs pulse followed by a 15 µs pulse, with a separation of 40 µs between the pulses.

C : The exclusive-OR output is a 15 µs pulse followed by a 40 µs pulse.

D : *The exclusive-OR output is a 20 µs pulse followed by a 15 µs pulse, followed by a 40 µs pulse.

### 5. The following waveform pattern is for a(n) ________.

Options

A : 2-input AND gate

B : 2-input OR gate

C : Exclusive-OR gate

D : None of the above

Options

A : 1

B : 2

C : 3

D : 4

### 9. Implementation of the Boolean expression results in ________.

Options

A : three AND gates, one OR gate

B : three AND gates, one NOT gate, one OR gate

C : three AND gates, one NOT gate, three OR gates

D : three AND gates, three OR gates

Options

A : 1

B : 2

C : 4

D : 5

### 2. The following waveform pattern is for a(n) ________.

Options

A : 2-input AND gate

B : 2-input OR gate

C : Exclusive-OR gate

D : None of the above

### 3. To implement the expression , it takes one OR gate and ________.

Options

A : three AND gates and three inverters

B : three AND gates and four inverters

C : three AND gates

D : one AND gate

Options

A : 1

B : 2

C : 3

D : 4

Options

A : True

B : False

C :

D :

Options

A : True

B : False

C :

D :

Options

A : True

B : False

C :

D :

Options

A : True

B : False

C :

D :

Options

A : True

B : False

C :

D :

Options

A : True

B : False

C :

D :

Options

A : True

B : False

C :

D :

Options

A : True

B : False

C :

D :

Options

A : True

B : False

C :

D :